In particular, the invention is applicable for the production of MOS or CMOS type integrated memory circuits.
An integrated EEPROM or EPROM memory is an integrated circuit including one actual memory portion known as a memory cell formed from a matrix of several electrically interconnected memory points and peripheral circuits used to control the memory points.
The invention solely deals with the actual memory portion.
The invention is adapted to any generation of drawing rules. It is neverthesless applicable to the embodiment of non-volatile memories with a high integration density allowing at least for the storage of 10 binary elements (.gtoreq.1 Mbits). In fact, this method makes it possible to reduce the surface of the memory point and thus mainly concerns memory cells with micronic or submicronic drawing rules and typically with floating gate widths of 0.6 .mu.m.
FIGS. 1 and 2 diagrammatically show one known type of EPROM memory cell embodied and drawn according to the conventional cells concept or with a T shape ; FIG. 1 is a top view and FIG. 2 is a longitudinal section along the direction II--II of FIG. 1.
For the purpose of simplification, this cell comprises per memory point 2 one floating gate 4 and one polycrystalline silicon control gate 6 stacked and isolated from each other by an intergate nonconductor 8, one gate nonconductor 10 inserted between the silicon substrate 12 and the floating gate 4, one source zone 14 diffused in the substrate 12, one drain zone 16 diffused in the substrate and one metallic electric half-contact 18. The reference D denotes all the diffused zones. Each drain zone 16 is common to two consecutive memory points.
Each memory point is the result of the crossing of a line of words 6a formed as the gate 6 in the upper polycrystalline silicon film and the line 18a of binary elements, hereinafter referred to as bits, embodied in the same film as the electric half-contact.
This type of memory point has been used for a large number of years from the generations of several kilobits up to the currently most advanced circuits of between 4 and 16 Mbits.
It main advantage resides in the wide experience acquired by EPROM memory manufacturers concerning this type of memory point and the foreseeable continuity when a memory generation advances to the next one.
However, with the increase in density integration, it is becoming increasingly difficult to make this memory evolve to having smaller dimensions as misalignments from level to level represent a considerable portion of its surface. For example, the memories of 1 Mbits embodied with conventional T memory points currently have a surface of about 45 mm2 for a memory point surface of between 18 and 20 .mu.m2, and memories of 4 Mbits have a surface of between about 70 and 80 mm2 for a memory point surface of between 9 and 10 .mu.m2.
Moreover, the traditional memory cell comprises one half-contact per memory point and for densities of several megabits, several millions of contacts are embodied in the circuit ; this then poses the problem of the density of defects concerning this type of metallization requiring significant control of the latter and possibly resulting in circuits malfunctioning on account of incorrect electric connection.
Several years ago, Boaz Eitan of the Wafer Scale Integration company proposed a new type of EPROM memory point known as a "Self-aligned Split gate EPROM". This memory point with a "split" gate is described in detail in the document U.S. Pat. No. 4,639,893 of Jan. 27, 1987.
FIGS. 3 and 4 diagrammatically show a known type of a "split gate" EPROM memory cell ; FIG. 3 is a top view and FIG. 4 is a longitudinal cutaway view along the line IV--IV of FIG. 3.
These figures show for each memory point 102 the floating gate 104 and the control gate 106 isolated by the intergate nonconductor 108, the gate nonconductor 110, and the source 114 and drain 116 zones diffused in the substrate 112. The gates 104 and 106 are made of polycrystalline silicon. The control gates 106 are constituted by the portion of the lines of words 106a opposite the floating gates 104.
This memory point 102 has the advantage of being formed via the crossing of lower polycrystalline silicon blocks 104 and lines of upper polycrystalline silicon lines of words 106a. In addition, this memory point has the advantage of not comprising any electric contact ; the contact of the bit lines (that is on the drain lines) is solely taken up every 16 or even 32 memory points.
This "split gate" memory point thus allows, with drawing rules identical to those of the T-shaped cells, a smaller surface of memory points to be obtained whilst considerably reducing the electric contact number in the memory plane. Thus, using this concept, the WSI company recently announced the embodiment of an EPROM memory of 1 Mbits, a surface of 26 mm2 with memory points of 9.5 .mu.m, then a memory of 4 Mbits, a surface of 65 mm2 embodied with the same memory point dimensions.
To this effect, reference may be made to the article in VLSI Symposium on Circuits, Kyoto, 1989 by S. All and al and entitled "A new staggered Virtual Ground array architecture Implemented in a 4Mb CMOS EPROM", pp. 35-36.
Moreover, the conception of the "split gate" memory point includes the embodiment of an access transistor connected in series with the double polycrystalline silicon gate.
In the rest of the description, the lower film of polycrystalline silicon shall be denoted as poly-1 and the upper polycrystalline silicon film as poly-2.
This access transistor is embodied by the separation zone 120 between the source zone 114, generally of the type N+, and the floating gate 104. This separation zone, controlled by the poly-2 gate of the line of words, modulates the effective electric length of the channel of the memory point according to the voltage applied to the poly-2.
When the voltage of the poly-2 gate (or line of words) is nil, this channel zone controlled by the poly-2 is blocked and the memory point does not operate. This makes it possible to considerably reduce the stray current of the memory points of a given progamming addressed line of bits but not situated on the same line of words ; this stray current is induced via the coupling of the drain with the floating gate (turn-on phenomenon).
This access transistor also makes it possible to envisage electric widths under the floating gate much smaller than those of the T memory points without running the risk of piercing between the source and drain of the memory points. Finally, it makes it possible to reduce the threshold voltage of the nonprogrammed memory points and thus increase their reading current.
However, this zone for separating the source and floating gate controlled by the line of words is embodied in the patent of Boaz Eitan by positioning a resin mask on the poly-1. If this masking is not critical for floating gate widths of about one micrometer, it becomes more difficult for submicronic floating gate widths (such as 0.6 .mu.m for the generation of a 16 Mbit memory).
The misalignment of this mask with respect to the floating gates has in fact a direct effect on the width of the source of each series transistor and on the electric length (or channel) of the series MOS transistor.
All the drawbacks mentioned above also exist in flash or non-flash type EEPROM memories which merely constitute special EPROMS.